1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular relates a method for fabricating a semiconductor device having dual-work function electrodes.
2. Description of the Related Art
Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with precision features and/or higher degrees of integration. For deep submicron technology, when the effective gate length of a MOS device decreases, leakage increases. Cause-and-effect examples of scaling trends include: (1) Reducing threshold voltage results in exponentially increasing sub-threshold leakage; (2) Gate edge direct tunneling results in tunneling leakage; (3) Reducing gate oxide thickness results in exponentially increasing gate-induced drain-leakage; and (4) Increasing lightly doped-drain (LDD) or pocket-doping concentration results in exponentially increasing bulk band-to-band-tunneling leakage. Thus, it is pertinent that leakage is precisely controlled without reducing voltage, following physical scaling of the MOS device. In addition, it is pertinent that the size of the device, such as thickness, and especially bottom thickness, of the gate structure is precisely controlled since the size of the device may dictate the channel length and the boundary of the source/drain.
A dual-work function gate MOS device comprises gate structures having different work functions. The dual-work function gate MOS device may usually comprise a gate oxide layer formed on a reactive region in a substrate. A polysilicon electrode may be formed on the gate oxide layer. Doping processes may be performed to the polysilicon electrode to form polysilicon electrodes having different work functions. Metal electrodes may be formed on the polysilicon electrodes. Top portions of the polysilicon electrodes and the metal electrodes may be patterned. Hard mask layers may be formed on sides and top surfaces of the patterned top portions of the polysilicon electrodes and metal electrodes to protect the patterned metal electrodes. The polysilicon electrode is doped with different dopants. Meanwhile, the work function and an etching rate of the polysilicon electrode may be different. The etching rate of the N-type doped polysilicon electrode may be faster than that of the P-type doped polysilicon electrode. Because the hard mask layers may be used to protect the patterned top portions of the polysilicon electrodes and metal electrodes, an etching process may be performed to remove bottom portions of the polysilicon electrodes. In one example, the bottom portion of the N-type doped polysilicon electrode may be etched to a desired width and the bottom portion of the P-type doped polysilicon electrode may be etched to a width bigger than the desired width. In another example, the bottom portion of the P-type doped polysilicon electrode may be etched to a desired width and the bottom portion of the N-type doped polysilicon electrode may be etched to a width smaller than the desired width. As a result, the polysilicon electrodes may be etched with undesired widths.
As described above, a method for fabricating a semiconductor device with dual-work function electrodes having desired widths is needed.